Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, and workstations. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.
The Rambus DDR3 interface solution incorporates Rambus innovations such as :
- FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock
- Calibrated output drivers
- On-die termination
- LabStation™ software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application
Other key interface features include :
- 800 to 1600 MHz data rates
- Support for DDR3 and DDR2 signaling modes
- On-chip phase-locked loop (PLL)
- On-chip delay-locked loop (DLL)
- Levelization support for fly-by command and address architecture
- Rambus FlexPhase™ based in-PHY module that provides characterization and testing capability in the production system
- Multi-drop bus and multi-rank module support for large capacity systems
- Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support
Rambus interface solutions provide a comprehensive architecture and system design, as well as design models and integration tools. Included in the solution are reference GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available.
Download the product brief, for more information about the Rambus DDR3 memory controller interface.
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