Terabyte Bandwidth Initiative

The Rambus Terabyte Bandwidth Initiative pioneers new memory signaling technologies useful for the development of a future memory architecture capable of delivering a terabyte per second of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC). This unparalleled memory bandwidth will enable future memory systems to benefit from an order of magnitude improvement in memory performance.

To achieve 1 TByte/s memory bandwidth, Rambus has developed fundamental innovations that include :

32X Data Rate - A new memory signaling technology which transmits 32 data bits per input clock cycle;
Fully Differential Memory Architecture (FDMA) - Providing the benefits of differential signaling on both the DQ (data) and C/A (command/address) channels;
FlexLink™ C/A - The industry's first full speed, scalable, point-to-point command/address link.

With these innovations and others developed through the Terabyte Bandwidth Initiative, Rambus will provide the foundation for a future memory architecture that offers increased performance, higher and scalable data bandwidth, area optimization, and enhanced signal integrity for gaming, graphics and multi-core computing applications of the next decade.

Background
Faster, multi-core processor-based systems require greatly increased memory performance over systems built around single-core processors. Without adequate bandwidth, memory systems will be the limiting factor in delivering the required performance desired in next-generation consumer and computing systems. As an example, graphics processors currently require as much as 128GBytes/s of memory bandwidth and are targeting 500 GBytes/s in the near future. The current generation of gaming systems uses 25-50 GBytes/s of memory bandwidth. Over the next 4-5 years, graphics and game consoles will push memory bandwidth needs towards 1 TByte/s.

Innovations
Rambus' innovative 32X Data Rate technology transmits 32 bits of data per clock cycle on each I/O. Conventional double data rate memory systems transfer two bits of data, per I/O, every clock cycle. While double data rate memory architectures can achieve a one gigabit per second transfer rate with a 500 MHz clock, 32X Data Rate enables an amazing 16Gbps signaling rate using the same 500 MHz clock.

The Rambus Terabyte Bandwidth Initiative also showcases the industry's first fully differential memory architecture (FDMA). In FDMA, both the data path and command/address channel employ differential signaling for robust communications between the memory controller and the DRAM. Rambus pioneered high speed differential memory signaling by transitioning the data signals from a single ended architecture to a differential scheme and used the signalling technique in its XDR™ DRAM design. Differential signaling inherently reduces interference noise, such as simultaneous switching output (SSO), crosstalk, and electromagnetic interference (EMI). Rambus has expanded the use of differential signaling in the Terabyte Bandwidth Initiative to include not only the data signals, but also the command/address signals, resulting in improved signal integrity and enhanced performance.

The third featured innovation of the Terabyte Bandwidth Initiative is FlexLink C/A. FlexLink C/A implements the industry's first full-speed, scalable, point-to-point command/address link. Operating at 16Gbps, FlexLink C/A reduces the required number of signal pins on both the DRAM and the memory controller. In contrast with a 1Gbit DDR2 device which requires 28 wires to connect the command/address link between the memory controller and the DRAM, FlexLink C/A implements a full 16Gbps command/address link with only two connections. This serial, scalable link also provides fine access and scalable capacity through a single command/address link per DRAM. FlexLink C/A's serial connectivity also delivers reduced area, power and pin count and lowers overall system costs.

Benefits
Through 32X, FDMA, FlexLink C/A and other innovations to be developed through the Terabyte Bandwidth Initiative, Rambus provides the foundation technologies for a terabyte memory architecture. A future SoC connected to 16 DRAM devices, each operating at 16Gbps with a 4-Byte wide interface, will achieve an impressive 1 terabyte per second of memory bandwidth. Through the Terabyte Bandwidth Initiative and the products that follow, Rambus enables its customers to develop a new generation of consumer and computing products that enrich the lives of consumers worldwide.