XIO2 Controller IO Cell

The XIO2 cell is a high-performance, power-efficient controller for XDR™2 DRAM devices. Using 16X Data Rate signaling technology, initial controller designs are capable of speeds of 9.6Gbps, with scalability up to 12.8Gbps. Each memory channel of the XIO2 controller cell can support a sustained bandwidth of up to 51.2GB/s per XDR2 DRAM device.

The XIO2 controller can be configured for multiple memory channels, each supporting from one to four XDR2 devices. This highly scalable architecture provides the necessary bandwidth and capacity for the demanding requirements of gaming, graphics and multi-core computing systems.

Each macro for the XIO2 controller IO cell is composed of 4 differential request (RQ) links, a control block (CTL) and a variable number of 8-bit data blocks (DQ). The RQ links provide address and control information to the memory subsystem. The CTL block performs register access, initialization, maintenance and testability functions. Each DQ is capable of transmitting and receiving data at up to 12.8Gbps.

Enhanced FlexPhase™ circuits allow arbitrary per-pin transmit and receive data phases on the DQ links and arbitrary per-pin transmit phases on the RQ links, eliminating the need for trace length matching of these high-speed signals. Employing the industry's first Fully Differential Memory Architecture (FDMA), the XIO2 cell operates the RQ and DQ links at full speed using ultra-low voltage Differential Rambus Signaling Level (DRSL). In combination, these Rambus innovations deliver the benefits of both improved signal integrity and lower power.