XDR™ Innovations

The Rambus XDR™ memory interface architecture consists of four building block technologies: Differential Rambus Signaling Level (DRSL), Octal Data Rate (ODR), FlexPhase™ de-skewing circuitry, and Dynamic Point-to-Point (DPP) technology.

• DRSL (Differential Rambus Signaling Level) is a low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO cell to XDR DRAM devices. XDR memory solutions also use the Rambus Signaling Level (RSL) standard developed originally for the RDRAM® memory interface, enabling up to 36 devices connected to the source-synchronous, bussed address and command signals.
• ODR (Octal Data Rate) is a technology that transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate). XDR data rates are scalable to 7.2Gbps.
• FlexPhase deskew circuits eliminate any systematic timing offsets between the bits of an XDR memory interface data bus. With a resolution of 2.5ps (at 3.2Gbps) and a maximum range of over 10 ns, the FlexPhase technology eliminates the need to match trace lengths on the board and package. FlexPhase also dynamically calibrates out on-chip clock skew, driver/receiver mismatch, and clock standing wave effects allowing lower system cost designs.
• Dynamic Point-to-Point (DPP) technology maintains the signal integrity benefits of point-to-point signaling on the data bus while providing the flexibility of capacity expansions with module upgrades. Memory modules can be dynamically reconfigured to support diferrent data bus widths, allowing a memory controller with a fixed data bus width to connect to a variable number of modules.

XDR™ Applications

The Rambus XDR™ memory interface solution satisfies the needs of many demanding applications such as game consoles, graphics, consumer electronics, multi-core computing, and servers. With the flexibility to provide more bandwidth at better power efficiency per device than competing technologies, XDR interfaces can also reduce overall systems costs for consumer products sensitive to total component count, and still meet the bandwidth requirements for performance driven applications. XDIMM modules provide an appropriate solution for high-capacity applications as well. No other memory technology provides the flexibility that XDR offers to system and chip designers across multiple markets.

Find out more detail on the application specific benefits of the XDR memory architecture for :

• Multi-core Computing
• Gaming and Graphics
• HDTV

DDR3

Rambus' memory controller interface solution for industry-standard DDR3 DRAMs features a fully integrated macro cell which provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, and workstations. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.

The Rambus DDR3 interface solution incorporates Rambus innovations such as :

• FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock
• Calibrated output drivers
• On-die termination
• LabStation™ software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application

Other key interface features include :

• 800 to 1600 MHz data rates
• Support for DDR3 and DDR2 signaling modes
• On-chip phase-locked loop (PLL)
• On-chip delay-locked loop (DLL)
• Levelization support for fly-by command and address architecture
• Rambus FlexPhase™ based in-PHY module that provides characterization and testing capability in the production system
• Multi-drop bus and multi-rank module support for large capacity systems
• Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support

Rambus interface solutions provide a comprehensive architecture and system design, as well as design models and integration tools. Included in the solution are reference GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available.

Download the product brief, for more information about the Rambus DDR3 memory controller interface.

Terabyte Bandwidth Initiative

The Rambus Terabyte Bandwidth Initiative pioneers new memory signaling technologies useful for the development of a future memory architecture capable of delivering a terabyte per second of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC). This unparalleled memory bandwidth will enable future memory systems to benefit from an order of magnitude improvement in memory performance.

To achieve 1 TByte/s memory bandwidth, Rambus has developed fundamental innovations that include :

32X Data Rate - A new memory signaling technology which transmits 32 data bits per input clock cycle;
Fully Differential Memory Architecture (FDMA) - Providing the benefits of differential signaling on both the DQ (data) and C/A (command/address) channels;
FlexLink™ C/A - The industry's first full speed, scalable, point-to-point command/address link.

With these innovations and others developed through the Terabyte Bandwidth Initiative, Rambus will provide the foundation for a future memory architecture that offers increased performance, higher and scalable data bandwidth, area optimization, and enhanced signal integrity for gaming, graphics and multi-core computing applications of the next decade.

Background
Faster, multi-core processor-based systems require greatly increased memory performance over systems built around single-core processors. Without adequate bandwidth, memory systems will be the limiting factor in delivering the required performance desired in next-generation consumer and computing systems. As an example, graphics processors currently require as much as 128GBytes/s of memory bandwidth and are targeting 500 GBytes/s in the near future. The current generation of gaming systems uses 25-50 GBytes/s of memory bandwidth. Over the next 4-5 years, graphics and game consoles will push memory bandwidth needs towards 1 TByte/s.

Innovations
Rambus' innovative 32X Data Rate technology transmits 32 bits of data per clock cycle on each I/O. Conventional double data rate memory systems transfer two bits of data, per I/O, every clock cycle. While double data rate memory architectures can achieve a one gigabit per second transfer rate with a 500 MHz clock, 32X Data Rate enables an amazing 16Gbps signaling rate using the same 500 MHz clock.

The Rambus Terabyte Bandwidth Initiative also showcases the industry's first fully differential memory architecture (FDMA). In FDMA, both the data path and command/address channel employ differential signaling for robust communications between the memory controller and the DRAM. Rambus pioneered high speed differential memory signaling by transitioning the data signals from a single ended architecture to a differential scheme and used the signalling technique in its XDR™ DRAM design. Differential signaling inherently reduces interference noise, such as simultaneous switching output (SSO), crosstalk, and electromagnetic interference (EMI). Rambus has expanded the use of differential signaling in the Terabyte Bandwidth Initiative to include not only the data signals, but also the command/address signals, resulting in improved signal integrity and enhanced performance.

The third featured innovation of the Terabyte Bandwidth Initiative is FlexLink C/A. FlexLink C/A implements the industry's first full-speed, scalable, point-to-point command/address link. Operating at 16Gbps, FlexLink C/A reduces the required number of signal pins on both the DRAM and the memory controller. In contrast with a 1Gbit DDR2 device which requires 28 wires to connect the command/address link between the memory controller and the DRAM, FlexLink C/A implements a full 16Gbps command/address link with only two connections. This serial, scalable link also provides fine access and scalable capacity through a single command/address link per DRAM. FlexLink C/A's serial connectivity also delivers reduced area, power and pin count and lowers overall system costs.

Benefits
Through 32X, FDMA, FlexLink C/A and other innovations to be developed through the Terabyte Bandwidth Initiative, Rambus provides the foundation technologies for a terabyte memory architecture. A future SoC connected to 16 DRAM devices, each operating at 16Gbps with a 4-Byte wide interface, will achieve an impressive 1 terabyte per second of memory bandwidth. Through the Terabyte Bandwidth Initiative and the products that follow, Rambus enables its customers to develop a new generation of consumer and computing products that enrich the lives of consumers worldwide.

Custom Solutions

In addition to our high-performance memory solutions and industry-standard partner solutions, Rambus also offers solutions customized for the design needs of the most challenging system implementations.

FlexIO™ processor bus
Multi-protocol serial link interfaces (FibreChannel, PCI Express® Gen1/Gen2, SATA, SPI-4.2, etc.)
Processor bus interfaces
Bi-modal DDR/XDR memory interfaces
Advanced backplane interfaces

Rambus' world-class engineering teams have years of experience developing technically innovative, silicon-proven solutions for computing, consumer, and networking applications. For more information about Rambus custom solutions, please contact our licensing team.

Partner Solutions

Rambus partners with industry-leading technology companies to deliver its high-speed interfaces to customers. Rambus digital logic and physical interfaces for PCI Express®, Fibre Channel, and other networking interfaces are available through Rambus partners.

PCI Express®

The PCI-SIG-compliant and interoperability-tested Rambus PCI Express solution has been implemented and shipped in numerous high-volume applications. Rambus digital core IP has adaptable application interfaces that minimize the amount of glue logic required for integration. Rambus PHY cells are delivered as complete serial communication cells, optimized for maximum production yield.

Rambus' newest PCI Express offering, the Rambus Gen2 Total Solution, provides high speed, point-to-point serial connectivity at 5 Gbps, as well as modular configuration to support 3 Gbps SATA. In addition to a PHY layer, the Gen2 solution is comprised of a digital controller and MAC layer, as well as in-system diagnostics and test features. Coupled with back end integration, validation, package and board design support, the Rambus Gen2 Total Solution enables quick deployment from concept to mass production.

The Rambus PCI Express Gen 1 solution provides I/O connectivity at 2.5 Gbps. Rambus' production proven digital controllers and PHY IP, available in 180nm, 130nm, 90nm and 65nm process geometries, remain the leading PCI Express solution with multiple entries on the PCI-SIG integrators list and targeted for multiple foundries and ASIC ODMs.

For more information regarding the Rambus PCI Express solution, please contact one of Rambus' partners :

Cadence
ChipX
GDA Technologies
PGC

Fibre Channel, Ethernet, RapidIO, and SPI-4.2

Rambus' Fibre Channel, Ethernet, RapidIO, and SPI-4.2 SerDes cells provide a range of solutions to meet the unique configurations and requirements of your communications system. Enabling you to build optimized form factors while minimizing power consumption and enabling high port densities. These cells are all silicon proven and have undergone stringent evaluation and characterization to ensure that they meet or exceed standards compliance.

For more information regarding Rambus' Fibre Channel, Ethernet, RapidIO, and SPI-4.2 SerDes cells, please contact one of Rambus' partners.

Cadence
eSilicon
GDA Technologies

RDRAM

RDRAM® Memory Architecture

RDRAM®, Rambus' first mainstream memory architecture, has been implemented in hundreds of millions of consumer, computing and networking productsfrom leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, Panasonic, SiS, Sony, Texas Instruments, and Toshiba.

RDRAM is no longer in high-volume production, but RDRAM components and RIMM modules are available from suppliers such as Samsung, Kingston, and Viking Components. For general information about RDRAM components and RIMM modules, see the RDRAM Frequently Asked Questions page.

Looking for a specific piece of RDRAM legacy documentation? Please let us know.

The XDR™memory architecture is Rambus' next-generation solution for high-performance, high-bandwidth consumer and computing applications. XDR DRAM is currently in volume production, and is available from Rambus partners Elpida, Samsung, and Qimonda.