XDR™2 Innovations

The Rambus XDR™2 memory architecture is the first to incorporate innovations from Rambus' Terabyte Bandwidth Initiative and builds on enhanced versions of key technologies already implemented in the award-winning XDR architecture. New technologies implemented for the first time in XDR2 memory include 16X Data Rate, Fully Differential Memory Architecture (FDMA), Enhanced FlexPhase™, Flexlink™ C/A, and Micro-threading.

• 16X Data Rate is a technology that transfers 16 bits of data per clock cycle, 8 times as many data bits as DDR (Double Data Rate) techniques used in many DRAMs today and twice the bit transfer rate of XDR memory. This technology allows the XDR2 memory system to run at data rates as high as 12.8Gbps at relatively low and economical system clock speeds.


• Fully Differential Memory Architecture (FDMA) is the industry’s first implementation of a memory architecture that incorporates differential signaling on all the key signal connections between the memory controller and the XDR2 DRAM. FDMA enables higher data rates, lower power, and improved signal integrity.


• Enhanced FlexPhase™ technology enables flexible phase relationships on data and command/address signals, allowing precise on-chip alignment of data with clock. Enhanced FlexPhase improves the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of over 6.4Gbps.


• Flexlink™ C/A is the industry's first full-speed, scalable, point-to-point command/address channel technology. Each FlexLink C/A link provides the command and address information to a DRAM using as few as a single, differential high-speed communications channel. This reduces pin count and area while enabling scalable capacity and flexible access granularity.


• Micro-threading is a technology that improves access efficiency for advanced applications. Micro-threading increases the useable bandwidth by logically partitioning a traditional 8-bank DRAM core into 16 independently addressable banks. Independent access to what are effectively 16 banks reduces both row and column access granularity and results in a significant performance increase for graphics and multi-core computing workloads.

XDR™2 Memory vs. GDDR5

THE FUTURE OF MEMORY

XDR™2 memory is the latest generation of the award-winning XDR memory architecture. Capable of unprecedented data rates of up to 12.8Gbps, XDR2 is the world's fastest memory solution. It delivers twice the peak bandwidth per device when compared to GDDR5 DRAM.

FAST AND SMART The XDR2 memory solution provides incredible bandwidth performance and does so at far lower power than GDDR5 memory. In fact, XDR2 consumes 30% less power than GDDR5 at equal bandwidth performance. Given equal power budget, XDR2 memory provides 50% more bandwidth than GDDR5. And at full speed, XDR2 DRAM deliver twice the bandwidth of GDDR5 devices.

BORN OF THE TERABYTE BANDWIDTH INITIATIVE XDR2 memory achieves this power and performance leadership through key Rambus innovations, many of which were developed through Rambus' Terabyte Bandwidth Initiative. The first to employ a Fully Differential Memory Architecture (FDMA), XDR2 memory has improved signal integrity and lower voltage swing versus single-ended signaling architectures such as GDDR5. Other innovations include Flexlink™ C/A, for more capacity scalability and flexible access granularity, and 16X Data Rate which allows the XDR2 memory to run at twice the data rate of GDDR5 with a clock running at about half the speed of the GDDR5 clock.

ROCK SOLID AND PIN EFFICIENT The Fully Differential Memory Architecture of XDR2 memory enables rock solid signal integrity at blindingly fast speeds. Differential signaling in combination with pin-efficient Flexlink C/A technology, enables XDR2 memory to deliver a breakthrough level of performance with fewer controller and DRAM pins than single-ended GDDR5 memory. Any way you look at it, speed, power, bandwidth, robustness or pin-efficiency, XDR2 memory is the best way to supercharge your next-generation graphics, gaming or multi-core computing design.

XDR™ Memory Architecture

The Rambus XDR™ memory architecture is a total memory system solution that achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs. Perfect for compute and consumer electronics applications, a single, 4-byte-wide, 6.4Gbps XDR DRAM component provides 25.6GB/s of peak memory bandwidth.

Key components enabling the breakthrough performance of the XDR memory architecture are :

• XDR DRAM is a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single device.
• XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FlexPhase™ technology that eliminates the need for trace length matching.
• XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
• XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.

XDR™ DRAM

Rambus XDR™ DRAM is a high-performance memory capable of 7.2Gbps data rates which can provide up to 28.8GB/s bandwidth with a single 4-byte-wide device. The roadmap for XDR DRAM extends to 8Gbps data rates which would provide 32GB/s of bandwidth per device. Designed for both high-bandwidth and cost-sensitive systems like graphics, compute and consumer electronics applications, XDR DRAM is a key component of the Rambus XDR memory architecture.

The XDR DRAM device uses an 8-bank DRAM core implemented in standard CMOS DRAM process technology and is currently in production at 512Mb and 1Gb densities. Unlike other DRAM devices, the x32 XDR DRAM device implements programmable width and supports data busses that are 16, 8, 4, and in some cases 2 bits wide. With this and many other architectural enhancements, the XDR DRAM device boasts much higher efficiency and throughput when compared with other memory technologies, thus making XDR memory the ideal solution for today’s bandwidth intensive compute and consumer electronics applications.

For more information on XDR DRAM please see the XDR™ DRAM 8x4Mx16 technical document.

XIO Controller IO Cell

The XIO cell is the high-performance, low-latency controller interface to XDR™ DRAM memory devices. Using Octal Data Rate (ODR) signaling at speeds of up to 7.2Gbps, the XIO IO cell can support bandwidths of up to 28.8GB/s from a single XDR DRAM device. The XIO can be configured to support multiple XDR devices thus providing the necessary memory bandwidth for demanding graphics, computing and consumer electronics applications. It can be used in tandem with the XMC memory controller or integrated with the customer’s logical controller design.

The XIO macro cell is composed of one or two 12-bit request bus blocks (RQ), one control block (CTL), and a variable number of 8-bit or 9-bit (for ECC support) data blocks (DQs). The RQ block provides address and control information to the memory subsystem. The CTL block performs register access, initialization, maintenance and testability functions. Each DQ block is capable of transmitting and receiving data at up to 7.2Gbps data rates. FlexPhase™ circuits allow arbitrary per-pin DQ transmit and receive data phases eliminating the need for system trace length matching. The RQ block generates single-ended signals, while the DQ blocks transmit and receive ultra low-voltage Differential Rambus Signaling Level (DRSL) signals.

For more information on the XIO controller IO cell please see the XDR™ IO Cell technical document.

XDIMM

The Rambus XDIMM is a high capacity memory module designed with high performance XDR™ DRAM devices. It provides the upgrade flexibility, capacity, and performance essential for servers, consumer electronics, and main memory applications. Operating at up to 6.4Gbps data rates, a single XDIMM provides many times the bandwidth of today's module-based systems while enabling multi-gigabyte capacities. With Rambus Dynamic Point-to-Point technology, XDIMMs can be installed in single or dual configurations while maintaining full system bandwidth and preserving the signal integrity of a true point-to-point topology. The Rambus XDIMM is part of the XDR memory system solution, allowing system and chip designers to integrate the world's fastest memory technology while eliminating interoperability and signal integrity problems.

XCG Clock Generator

The XCG Clock Generator provides the necessary clock signals to support an XDR memory system. It is an off-the-shelf solution provided by several leading IC companies for a broad range of high performance clocking applications. Guaranteed to provide clocks that meet specifications for both the XIO Cell and the XDR DRAM device, the XCG provides four programmable differential outputs using a reference input clock of 100MHz or 133MHz. The XCG also supports spread spectrum modulation, reducing the EMI generated from the clock distribution network.